Media Alert: Connect, Share and Discuss the Latest Design and Verification Best Practices at the 2017 Cadence Jasper User Group Conference

SAN JOSE, Calif., Oct. 30, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) will host its annual Jasper^® User Group Conference on November 7 and 8 at the Cadence headquarters in San Jose, California. The Jasper User Group Conference connects designers, verification engineers and engineering managers from around the world to share the latest design and verification practices based on Cadence^® JasperGold^® formal verification technologies and methodologies.

For more information and to register for the conference, visit www.cadence.com/jug2017.

WHAT: The Jasper User Group Conference offers:

• Keynote: Formal Lead—An Interesting Career Path, presented by M V Achutha Kiran Kumar, Renowned Formal Expert and Co-author, Formal Verification: An Essential Toolkit for Modern VLSI Design.
• In-depth user presentations covering core technologies, applications and flows such as:
• Coverage-Driven Formal Verification Signoff of CCIX Design, presented by the Cadence IP Group
• Formal Verification by the Book: ISA Formal at Arm, presented by Arm
• Automatic Hazard Detection Using Formal Methods, presented by Texas Instruments
• Divide and Conquer the Valley of Death, presented by Hewlett Packard Enterprise
• A New Use for JasperGold FPV App: Closing Static Timing Analysis, presented by Analog Devices
• Deadlock Hunting in a Network Processor Using JasperGold FPV App, presented by Trend Micro
• The Evolution of Formal Verification Signoff, presented by Oski Technology
• How Formal Is Helping Us Achieve Our Safety Goals for Software Test Library Development on Arm^® CPUs, presented by Arm
• A Formal Approach to Early RTL Checking to Improve Verification Efficiency, presented by Texas Instruments
• Formal Property Verification and Deep Bug Hunting to Complement Simulation on a Critical Unit Within a GPU, presented by Samsung
• Architectural Formal Verification of Coherency Manager, presented by NVIDIA
• A Cadence Formal Technology Update by Ziyad Hanna, Cadence
• Demonstrations showcasing the latest formal verification products from Cadence
• Networking reception
• Best presentation award granted to the presenter with the highest session ratings

WHEN: JUG is scheduled for November 7-8, 2017

WHERE: Cadence San Jose Auditorium, Building 10, 2655 Seely Avenue, San Jose, CA

About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com

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SOURCE Cadence Design Systems, Inc.